Electronic chip package with reduced contact pad pitch

An apparatus and method, the apparatus includes an electronic chip package including an electronic chip having a first and a second contact pad formed thereon, a first dielectric layer coupled to the electronic chip, a second dielectric layer coupled to the first dielectric layer such that a dielectric boundary lies therebetween, a first and a second cover pad positioned along the dielectric boundary, a metal interconnect formed along a first multi-layer via and coupled to the first cover pad and contact pad, and a metal interconnect formed along a second multi-layer via and coupled to the second cover pad and contact pad. The first multi-layer via extends through the second dielectric layer, the first cover pad, and the first dielectric layer to the first contact pad. The second multi-layer via extends through the second dielectric layer, the second cover pad, and the first dielectric layer to the second contact pad.