Metal oxide semiconductor transistor with reduced gate height, and related fabrication methods
A metal oxide semiconductor transistor device having a reduced gate height is provided. One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain recesses formed in the semiconductor ma...
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creator | PAL ROHIT YANG FRANK BIN LUNING SCOTT |
description | A metal oxide semiconductor transistor device having a reduced gate height is provided. One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain recesses formed in the semiconductor material adjacent to the gate structure, such that remaining semiconductor material is located below the source/drain recesses. The device also includes shallow source/drain implant regions formed in the remaining semiconductor material, and epitaxially grown, in situ doped, semiconductor material in the source/drain recesses. |
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One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain recesses formed in the semiconductor material adjacent to the gate structure, such that remaining semiconductor material is located below the source/drain recesses. The device also includes shallow source/drain implant regions formed in the remaining semiconductor material, and epitaxially grown, in situ doped, semiconductor material in the source/drain recesses.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2011</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20110614&DB=EPODOC&CC=US&NR=7960229B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76419</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20110614&DB=EPODOC&CC=US&NR=7960229B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>PAL ROHIT</creatorcontrib><creatorcontrib>YANG FRANK BIN</creatorcontrib><creatorcontrib>LUNING SCOTT</creatorcontrib><title>Metal oxide semiconductor transistor with reduced gate height, and related fabrication methods</title><description>A metal oxide semiconductor transistor device having a reduced gate height is provided. One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain recesses formed in the semiconductor material adjacent to the gate structure, such that remaining semiconductor material is located below the source/drain recesses. The device also includes shallow source/drain implant regions formed in the remaining semiconductor material, and epitaxially grown, in situ doped, semiconductor material in the source/drain recesses.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2011</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNikEKwjAQRbtxIeod5gAKUkHptqK4caVuLWPy2wykSUlG9PhW8ACu_uO9Py3uZyh7im-xoIxeTAz2aTQm0sQhS_7iS9RRwhhgqWMFOUjndEkc7Bj8qCy1_EhiWCUG6qEu2jwvJi37jMVvZwUdD9f9aYUhNsgDGwRoc7vsqu26LKu63Pxx-QAGITzJ</recordid><startdate>20110614</startdate><enddate>20110614</enddate><creator>PAL ROHIT</creator><creator>YANG FRANK BIN</creator><creator>LUNING SCOTT</creator><scope>EVB</scope></search><sort><creationdate>20110614</creationdate><title>Metal oxide semiconductor transistor with reduced gate height, and related fabrication methods</title><author>PAL ROHIT ; YANG FRANK BIN ; LUNING SCOTT</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7960229B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2011</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>PAL ROHIT</creatorcontrib><creatorcontrib>YANG FRANK BIN</creatorcontrib><creatorcontrib>LUNING SCOTT</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>PAL ROHIT</au><au>YANG FRANK BIN</au><au>LUNING SCOTT</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Metal oxide semiconductor transistor with reduced gate height, and related fabrication methods</title><date>2011-06-14</date><risdate>2011</risdate><abstract>A metal oxide semiconductor transistor device having a reduced gate height is provided. One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain recesses formed in the semiconductor material adjacent to the gate structure, such that remaining semiconductor material is located below the source/drain recesses. The device also includes shallow source/drain implant regions formed in the remaining semiconductor material, and epitaxially grown, in situ doped, semiconductor material in the source/drain recesses.</abstract><oa>free_for_read</oa></addata></record> |
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title | Metal oxide semiconductor transistor with reduced gate height, and related fabrication methods |
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