Address translation system for use in a simulation environment

Methods and systems for simulation of a testable system are provided in which a virtual testable system is used. One method includes inputting a system definition file into a translation utility, where the system definition file includes a plurality of physical addresses required for execution of th...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: WOIT CORNELIA, SCHADE OLIVER, CATES JAMEY JOSEPH, FOSTER TIMOTHY W
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:Methods and systems for simulation of a testable system are provided in which a virtual testable system is used. One method includes inputting a system definition file into a translation utility, where the system definition file includes a plurality of physical addresses required for execution of the system definition file in the testable system. The method also includes inputting a memory map file into the translation utility, the memory map representing a virtual memory space for a virtual testable system. The method further includes generating virtual translation information by translating the physical addresses into virtual addresses using the memory map file.