Frame buffer tag addressing for partitioned graphics memory supporting non-power of two number of memory elements

A graphics system has virtual memory and a partitioned graphics memory that supports having an non-power of two number of dynamic random access memories (DRAMs). The graphics system utilizes page table entries to support addressing Tag RAMs used to store tag bits indicative of a compression status.

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Bibliographische Detailangaben
1. Verfasser:	VAN DYKE JAMES M
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING IMAGE DATA PROCESSING OR GENERATION, IN GENERAL PHYSICS
Online-Zugang:	Volltext bestellen
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Beschreibung
Zusammenfassung:	A graphics system has virtual memory and a partitioned graphics memory that supports having an non-power of two number of dynamic random access memories (DRAMs). The graphics system utilizes page table entries to support addressing Tag RAMs used to store tag bits indicative of a compression status.