Latch and DFF design with improved soft error rate and a method of operating a DFF

A single-path latch, a dual-path latch, a method of operating a DFF and a library of cells. In one embodiment, the single-path latch includes: (1) a passgate coupled to the data input, (2) a feedback path coupled to the passgate, the data output coupled thereto and (3) tristate circuitry coupled to the passgate and having a single transistor pair of opposite conductivity coupled to Boolean logic gates, the Boolean logic gates configured to control operation of the single transistor pair based on the data input and a pulse clock signal to drive the feedbacks path.