Scan chain cell with delay testing capability

A scan chain cell 24 is provided with a built-in delay testing capability. An inverter 32 generates an inverted form of the cell output which is available within the scan chain cell 24 for rapid use in forming a transition at the cell output Q. Clock gating circuitry 36, 38 is responsive to a hold signal to block the functional path 34, 26, 28 through the scan chain cell and hold the output signal when desired. The functional clock clk may be clocked twice at speed to trigger capture of the results of processing the output of the scan chain cell 24 for the non-inverted value followed by the (internally generated) inverted value, i.e. a signal transition. In this way delay testing of the functional circuitry 18 can be performed.