Timing analysis of a mapped logic design using physical delays

Approaches for determining a static timing analysis of a logic design are disclosed. Physical delay arcs of a plurality of physical elements of an integrated circuit specify respective propagation delays from inputs of the physical elements to outputs of the physical elements. Logic components of th...

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Bibliographische Detailangaben
Hauptverfasser:	JHA PRADIP KUMAR, GAITONDE DINESH D, LI YAU-TSUN STEVEN
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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Beschreibung
Zusammenfassung:	Approaches for determining a static timing analysis of a logic design are disclosed. Physical delay arcs of a plurality of physical elements of an integrated circuit specify respective propagation delays from inputs of the physical elements to outputs of the physical elements. Logic components of the logic design are mapped to selected ones of the physical components of the physical elements. For each of the logic components, the logic delay arcs are determined from the physical delay arcs. Each logic delay arc for each logic component specifies a propagation delay from an input of the logic component to an output of the logic component. A static timing analysis of the logic components is performed using the logic delay arc, and data from the timing analysis is output.