Methods for practical worst test definition and debug during block based statistical static timing analysis

Methods for practical worst test definition and debug during block based statistical static timing analysis

Methods for analyzing timing of an integrated circuit using block-based static statistical timing analysis and for practical worst test definition and debug. The method includes building a timing graph, determining a slack for each of the nodes in the timing graph, and identifying a statistically wo...

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Bibliographische Detailangaben
Hauptverfasser: HEMMETT JEFFREY G, FOREMAN ERIC A, BUCK NATHAN C, GREGERSON JAMES C
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:Methods for analyzing timing of an integrated circuit using block-based static statistical timing analysis and for practical worst test definition and debug. The method includes building a timing graph, determining a slack for each of the nodes in the timing graph, and identifying a statistically worst slack for at least one of the nodes. The method further includes replacing this statistically worst slack with a proxy worst slack.