Patching device for a processor

A code patching device is provided for use with a processor having a read-only memory which stores instruction code and a further memory for storing patch code. A plurality of patch address registers each store an address, in the read-only memory, at which a patch is to be performed. A comparator compares the address of the read-only memory that is being accessed by the processor with the addresses stored in the registers. A control unit selects between code from the read-only memory or patch code from the further memory depending on the comparison. The code patching device can replace, on-the-fly, erroneous lines of code from the read-only memory by corrected ones. During an initialization process the patch code is loaded into the further memory and the registers are loaded with the addresses which require patching.