Implementing integrated circuit yield estimation using voronoi diagrams

A method for implementing integrated circuit yield estimation includes computing Voronoi regions for an original integrated circuit layout; for each bisector segment of the Voronoi regions and one or more failure mechanisms, computing a failure probability based on geometric parameters of correspond...

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Bibliographische Detailangaben

Hauptverfasser:	O'NEIL PATRICIA A, MONKOWSKI MICHAEL D
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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