Implementing integrated circuit yield estimation using voronoi diagrams

A method for implementing integrated circuit yield estimation includes computing Voronoi regions for an original integrated circuit layout; for each bisector segment of the Voronoi regions and one or more failure mechanisms, computing a failure probability based on geometric parameters of corresponding Voronoi edge regions associated with the bisector segment, using pre-computed failure probabilities as a function of edge orientation and spacing for the failure mechanisms; for each segment of a design edge bounded by bisectors, computing a change in the failure probability based on the geometric parameters of the Voronoi regions, using pre-computed change in failure probabilities for the failure mechanisms; encoding the computed failure probabilities for each Voronoi region in a manner suitable for visual differentiation by a user; and encoding the computed change in failure probabilities by directional displacement of a layout edge segment that would result in a decrease in failure probability.