All digital frequency-locked loop circuit method for clock generation in multicore microprocessor systems

A (DFLL) circuit residing on a local core of a multi-core microprocessor for generating a local core clock with a frequency for driving the local core includes a micro-controller configured to receive core characterizing digital data; a ring oscillator configured to generate the local core clock for the local core, and having a delay chain disposed between an output and a feedback input of the ring oscillator, the delay chain having delay taps each receiving the local core clock enabling quantum changes in the frequency of the local core clock; and a counter device configured to continually validate the frequency by generating a digital signal representative of the frequency to the micro-controller, the micro-controller compares the frequency of the local core clock to a desired clock frequency, and selects one of the delay taps based on the comparison to adjust the frequency value of the local core clock.