Programmable power down scheme for embedded memory block

An integrated circuit configured to selectively provide power to used portions of a memory array is presented. The integrated circuit includes an array of memory cells for storing digital data and a power bus interconnecting structure. The power bus interconnecting structure includes global power bu...

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Bibliographische Detailangaben

Hauptverfasser:	KOAY WEI YEE, CHIENG NGEE KIAT, LIM MEI CHING, LAI YAU KOK, OOI TENG CHOW
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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