Programmable power down scheme for embedded memory block

An integrated circuit configured to selectively provide power to used portions of a memory array is presented. The integrated circuit includes an array of memory cells for storing digital data and a power bus interconnecting structure. The power bus interconnecting structure includes global power buses in communication with local power buses through programmable vias. The array of memory cells are remapped so that unused column portions of the memory array become unused row portions of the memory array. The programmable vias are selectively located during design of the integrated circuit, providing power to the used portions of the memory array.