Method and circuit for processing data in communication networks

A method and circuitry for detecting a pattern in received data such as the A1A2 boundary in a SONET frame after deserialization. Two consecutive pluralities of bytes of incoming data are stored and compared with the A1 and A2 values (or bit shifted versions of the A1 and A2 values) until the bounda...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser:	ANNADURAI ANDY, HAN FENG, TSU CHRIS
Format:	Patent
Sprache:	eng
Schlagworte:	ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS MULTIPLEX COMMUNICATION TECHNICAL SUBJECTS COVERED BY FORMER USPC TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Beschreibung
Zusammenfassung:	A method and circuitry for detecting a pattern in received data such as the A1A2 boundary in a SONET frame after deserialization. Two consecutive pluralities of bytes of incoming data are stored and compared with the A1 and A2 values (or bit shifted versions of the A1 and A2 values) until the boundary is detected. The data are then bit shifted so that every byte on the bus is either A2 or A1. A new aligned data bus is then formed such that the last A1 bit occurs on the data bus for a given clock cycle and the first A2 bit occurs on the data bus during the next clock cycle.