Embedded chip package structure

An embedded chip package process is disclosed. First, a first substrate having a first patterned circuit layer thereon is provided. Then, a first chip is disposed on the first patterned circuit layer and electrically connected to the first patterned circuit layer. A second substrate having a second patterned circuit layer thereon is provided. A second chip is disposed on the second patterned circuit layer and electrically connected to the second patterned circuit layer. Afterwards, a dielectric material layer is formed and covers the first chip and the first patterned circuit layer. Then, a compression process is performed to cover the second substrate over the dielectric material layer so that the second patterned circuit layer and the second chip on the second substrate are embedded into the dielectric material layer.