Field programmable gate array utilizing dedicated memory stacks in a vertical layer format

Field programmable gate array utilizing dedicated memory stacks in a vertical layer format

A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word wid...

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Bibliographische Detailangaben
Hauptverfasser: GANN KEITH D, BOYD W. ERIC, CARLSON RANDOLPH S, OZGUZ VOLKAN H, LEON JOHN
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
BASIC ELECTRONIC CIRCUITRY
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PULSE TECHNIQUE
SEMICONDUCTOR DEVICES
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Zusammenfassung:A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m.times.N where m is the number of word width bits per memory chip and N is the number of memory chips.