Mechanism to generate logically dedicated read and write channels in a memory controller

Mechanism to generate logically dedicated read and write channels in a memory controller

According to one embodiment, a system is disclosed. The system includes a memory controller to schedule read commands to frames via a first dedicated command slot and to schedule write commands and corresponding data to frames via a dedicated second or third command slot.

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Bibliographische Detailangaben
Hauptverfasser: SUBASHCHANDRABOSE RAMESH, MOHANTY ANUPAM, AGARWAL RAJAT
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:According to one embodiment, a system is disclosed. The system includes a memory controller to schedule read commands to frames via a first dedicated command slot and to schedule write commands and corresponding data to frames via a dedicated second or third command slot.