Memory device with mode-selectable prefetch and clock-to-core timing

In a memory device, either a first portion or a second, smaller portion of data retrieved from a storage array is loaded into a data buffer in accordance with a prefetch mode selection and then output from the memory device via a signaling interface. A value that indicates a minimum number of cycles of a clock signal that are to transpire between successive accesses to any one of the storage resources may be received and stored within a configuration circuit of the memory device. If the value indicates a number of clock cycles, N, that is less than a threshold number, the memory device may transfer data associated with a first address between the signaling interface and the data buffer during each of N cycles of the clock signal. If N is greater than or equal to the threshold number, the memory device may transfer the data associated with the first address between the signaling interface and the storage buffer during each of X cycles of the clock signal, and then transfer data associated with the second address between the signaling interface and the storage buffer during each of X cycles of the clock signal, where X is an integer value less than N.