Method and apparatus for automatic configuration of multiple on-chip interconnects
A method and apparatus for automatic configuration of multiple on-chip interconnects have been described. In one embodiment, the invention reduces the configuration time of several on-chip network features, and also ensures that these features are configured correctly to minimize errors in a design.
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | A method and apparatus for automatic configuration of multiple on-chip interconnects have been described. In one embodiment, the invention reduces the configuration time of several on-chip network features, and also ensures that these features are configured correctly to minimize errors in a design. |
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