Hermetic packaging and method of manufacture and use therefore

A system and method for manufacturing micro cavity packaging enclosure at the wafer level using MEMS (MicroElectroMechanical Systems) process, wherein micro cavities are formed from epoxy-bonded single-crystalline silicon wafer as its cap, epoxy and deposited metal or insulator as at least part of i...

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Bibliographische Detailangaben
1. Verfasser:	WAN CHANG-FENG
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MEASURING MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER,MECHANICAL EFFICIENCY, OR FLUID PRESSURE MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICALDEVICES MICROSTRUCTURAL TECHNOLOGY PERFORMING OPERATIONS PHYSICS PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTUREOR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS SEMICONDUCTOR DEVICES TESTING TRANSPORTING
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Beschreibung
Zusammenfassung:	A system and method for manufacturing micro cavity packaging enclosure at the wafer level using MEMS (MicroElectroMechanical Systems) process, wherein micro cavities are formed from epoxy-bonded single-crystalline silicon wafer as its cap, epoxy and deposited metal or insulator as at least part of its sidewall, on substrate wafers.