Processor-controlled timing generator for multiple image sensors

A versatile analog front end and timing generator (AFE/TG) integrated circuit is capable of supplying horizontal and vertical timing signals to a large number of disparate image sensors. In a first novel aspect, the AFE/TG includes an output mode wherein multiple identical AFE/TGs output digitized sensor data to a single digital image processor (DIP) without intervening multiplexing circuitry. In a second novel aspect, the AFE/TG includes a processor that executes a program. Execution of the program controls the detailed timing of horizontal and vertical timing signals output from the AFE/TG. At boot time, the program is loaded into the AFE/TG via a serial bus. In a third novel aspect, the processor is clocked by a clock signal with a relatively long clock period. A DLL and associated set/reset circuitry allows the processor to generate and control timing signals with a resolution substantially greater than clock period of the processor.