Computer-aided-design tools for reducing power consumption in programmable logic devices

Methods and apparatus for designing and producing programmable logic devices are provided. A logic design system may be used to analyze various implementations of a desired logic design for a programmable logic device integrated circuit. The logic design system may be used to produce configuration data for the programmable logic device in accordance with an implementation that minimizes power consumption by the programmable logic device. The programmable logic device contains logic blocks that are used to implement the desired logic design and logic blocks that are unused. Dynamic power consumption can be minimized by identifying which configuration data settings reduce the amount of signal toggling in the unused logic blocks and routing, and by minimizing the capacitance of resources that do toggle. Clock tree power consumption can be reduced by evaluating multiple potential logic design implementations using a strictly concave cost function.