Method and apparatus for testing integrated circuits for susceptibility to latch-up
In an example embodiment, there is a test module for testing the susceptibility of an integrated circuit design to latch-up. The test module comprises a plurality of test blocks, connected in parallel. Each test block includes an injector block for applying a stress current of voltage to the respect...
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| creator | CAPPON PAUL H DE JONG PETER C SCARPA ANDREA SMEDES TAEDE |
| description | In an example embodiment, there is a test module for testing the susceptibility of an integrated circuit design to latch-up. The test module comprises a plurality of test blocks, connected in parallel. Each test block includes an injector block for applying a stress current of voltage to the respective test block and a plurality of sensor blocks located at successively increasing distances from the respective injector block. Each sensor block includes a PNPN latch-up test structure. The present invention combines the respective advantages of IC stress current testing and latch-up parameter measurement using a standard PNPN latch-up test structure. |
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The present invention combines the respective advantages of IC stress current testing and latch-up parameter measurement using a standard PNPN latch-up test structure.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2009</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNijEKwkAQRbexEPUOc4FAUIKkVRQbq2gdxs0kGVh2h53Zwtsb0ANYfB6899euu5PNaQCMy0QwoxWFMWUwUuM4AUejadE0gOfsC9u3a1FPYvziwPYGSxDQ_FwV2brViEFp9-PGwfXyON8qktSTCnqKZP2zOzZN3bb1aX_44_IBMIo4zg</recordid><startdate>20090623</startdate><enddate>20090623</enddate><creator>CAPPON PAUL H</creator><creator>DE JONG PETER C</creator><creator>SCARPA ANDREA</creator><creator>SMEDES TAEDE</creator><scope>EVB</scope></search><sort><creationdate>20090623</creationdate><title>Method and apparatus for testing integrated circuits for susceptibility to latch-up</title><author>CAPPON PAUL H ; DE JONG PETER C ; SCARPA ANDREA ; SMEDES TAEDE</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7550990B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2009</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>CAPPON PAUL H</creatorcontrib><creatorcontrib>DE JONG PETER C</creatorcontrib><creatorcontrib>SCARPA ANDREA</creatorcontrib><creatorcontrib>SMEDES TAEDE</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CAPPON PAUL H</au><au>DE JONG PETER C</au><au>SCARPA ANDREA</au><au>SMEDES TAEDE</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method and apparatus for testing integrated circuits for susceptibility to latch-up</title><date>2009-06-23</date><risdate>2009</risdate><abstract>In an example embodiment, there is a test module for testing the susceptibility of an integrated circuit design to latch-up. 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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS SEMICONDUCTOR DEVICES TESTING |
| title | Method and apparatus for testing integrated circuits for susceptibility to latch-up |
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