Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage

A method for designing an integrated circuit is disclosed. The method generally comprises the steps of (A) splitting a design layout of the integrated circuit into a plurality of tiles, (B) adding a plurality of tie-to cells to the design layout, wherein at least one of the tie-to cells generating a tie-to signal at a particular logical level is added into each of the tiles having at least one gate with an input fixed to the particular logical level and (C) routing the tie-to signal to each of the inputs within each of the tiles.