Circuit for and method of preventing an error in a flip-flop
A circuit for preventing an error in a flip-flop is disclosed. The circuit comprises an input circuit for receiving input data; a circuit for generating true and complement data associated with each of the input data and redundant data at predetermined nodes of the circuit; and a plurality of invert...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | A circuit for preventing an error in a flip-flop is disclosed. The circuit comprises an input circuit for receiving input data; a circuit for generating true and complement data associated with each of the input data and redundant data at predetermined nodes of the circuit; and a plurality of inverters each controlled by an associated node, wherein an inverter node of each inverter of the plurality of inverters is coupled to a separate node of the predetermined nodes. A method of preventing an error in a flip-flop is also disclosed. |
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