Carry-skip adder having merged carry-skip cells with sum cells

A multi-bit adder includes a carry chain, a carry-skip network, sum cells, and a carry-sum cell. The carry chain propagates, generates, or kills carry-in bits. The carry-skip network is coupled to the carry chain to selectively skip the carry-in bits over at least one portion of the carry chain. The sum cells are coupled along the carry chain to sum the carry-in bits with corresponding bits of two operands to generate a multi-bit resultant. The carry-sum cell is coupled to receive one of the carry-in bits to a single intermediate bit position on the carry chain and to generate one bit of the multi-bit resultant having a more significant bit position than the single intermediate bit position.