Reset detector

A reset detector is disclosed, which monitors the hardware reset of the subsystem(s) involved, in order to verify that the hardware reset has placed the subsystem in a correct reset state. Thus, in order to verify that an initial hardware reset has occurred, the subsystem software (e.g., during boot-up) detects the initial reset status of the reset detector, and blocks any additional reset attempts that may occur. In other words, the reset detector verifies that the subsystem hardware has been reset correctly, before the application software can proceed into an operational mode. An example reset detector circuit is disclosed, which includes a local reset signal generated by an RC delay circuit. The local reset signal is isolated from the system reset function, which allows the reset detector circuit to be initialized and reset separately from the system reset. Once the reset detector circuit is initialized, it monitors the system reset request line. Assuming that a system reset request is an active low signal, the reset detector circuit detects the "rising edge" of such a system reset signal, and latches this condition so that it can be reported to the host software. If a second or subsequent system reset request occurs, the reset detector circuit detects the "falling edge" of the system reset signal, and latches this condition for subsequent house-keeping and error reporting purposes. Also, the reset detector circuit disclosed can be designed to be re-initialized by the system software subsequent to boot-up if such a reset condition is desired. Furthermore, the RC Time Constant of the local passive reset circuit can be sized to evaluate a minimum length of time that an external reset signal must be held low.