Efficient muxing scheme to allow for bypass and array access

A method and apparatus for using a 2:1 MUX to control read access, data bypass, and page size bypass in a memory array. The mechanism of the present invention reduces the 3:1 MUX normally required to manage these three functions to a 2:1 MUX.

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Bibliographische Detailangaben
Hauptverfasser:	BIANCHI ANDREW JAMES, KHAN MASOOD AHMED, FLUHR ERIC JASON, LEE MICHAEL JU HYEOK, SEEWANN EDELMAR
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS STATIC STORES TESTING
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Beschreibung
Zusammenfassung:	A method and apparatus for using a 2:1 MUX to control read access, data bypass, and page size bypass in a memory array. The mechanism of the present invention reduces the 3:1 MUX normally required to manage these three functions to a 2:1 MUX.