Parallel input/output self-test circuit and method

Parallel input/output self-test circuit and method

A parallel data transmission test system can include a receiver section ( 100 ) having input selector circuits ( 104 -O to 104 -N) that provide a received test data to logic adjust circuits ( 106 -O to 106 -N) that "logically align" multiple incoming test values to remove intentionally int...

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Bibliographische Detailangaben
Hauptverfasser: KRISHNAN GOPALAKRISHNAN PERUR, VADLAMANI ESWAR, MUNDAY TARJINDER SINGH
Format: Patent
Sprache:eng
Schlagworte:
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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Beschreibung
Zusammenfassung:A parallel data transmission test system can include a receiver section ( 100 ) having input selector circuits ( 104 -O to 104 -N) that provide a received test data to logic adjust circuits ( 106 -O to 106 -N) that "logically align" multiple incoming test values to remove intentionally introduced logic difference (e.g., inversion) with respect to one another. Result combining circuit ( 108 ) can logically combine output data values and provide a resulting sequence to a pattern sequence test circuit ( 110 ).