Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS

Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS

An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is...

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Bibliographische Detailangaben
Hauptverfasser: LEE YONG MENG, LAI CHUNG WOH, SUDIJONO JOHN, HSIA LIANG CHOO, TEH YOUNG WAY, LIN WENHE, TAN WEE LENG, LIM KHEE YONG, KOH HUI PENG
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have an silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.