Apparatus, system, and method for modifying memory voltage and performance based on a measure of memory device stress
An apparatus, system, and method are disclosed for modifying memory device timing and voltage. A detection module detects a change of memory device stress. A timing modification module modifies the memory device timing in response to the change of the memory device stress. In addition, a voltage mod...
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creator | ROUMBAKIS MENAS PHAM NAM HUU CASES MOISES DE ARAUJO DANIEL N |
description | An apparatus, system, and method are disclosed for modifying memory device timing and voltage. A detection module detects a change of memory device stress. A timing modification module modifies the memory device timing in response to the change of the memory device stress. In addition, a voltage modification module modifies the memory device voltage in response to the change of the memory device stress. In one embodiment, a processor pause module pauses the operation of a processor module while the timing modification module modifies the memory device timing and the voltage modification module modifies the memory device voltage. |
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A detection module detects a change of memory device stress. A timing modification module modifies the memory device timing in response to the change of the memory device stress. In addition, a voltage modification module modifies the memory device voltage in response to the change of the memory device stress. In one embodiment, a processor pause module pauses the operation of a processor module while the timing modification module modifies the memory device timing and the voltage modification module modifies the memory device voltage.</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; PULSE TECHNIQUE ; STATIC STORES</subject><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20081028&DB=EPODOC&CC=US&NR=7444490B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20081028&DB=EPODOC&CC=US&NR=7444490B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ROUMBAKIS MENAS</creatorcontrib><creatorcontrib>PHAM NAM HUU</creatorcontrib><creatorcontrib>CASES MOISES</creatorcontrib><creatorcontrib>DE ARAUJO DANIEL N</creatorcontrib><title>Apparatus, system, and method for modifying memory voltage and performance based on a measure of memory device stress</title><description>An apparatus, system, and method are disclosed for modifying memory device timing and voltage. A detection module detects a change of memory device stress. A timing modification module modifies the memory device timing in response to the change of the memory device stress. In addition, a voltage modification module modifies the memory device voltage in response to the change of the memory device stress. In one embodiment, a processor pause module pauses the operation of a processor module while the timing modification module modifies the memory device timing and the voltage modification module modifies the memory device voltage.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>PULSE TECHNIQUE</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNy8EKwjAQBNBePIj6D_sBFUQF8aiieFfPZW0mtdBkQzYt9O8NonfnMjC8mRb9IQSOnHotSUdNcCWxN-SQXmLISiQnprVj65s8OokjDdIlbvBxATEbx74GPVlhSDxxlqx9BIn9nQyGNhtNEarzYmK5Uyy-PSvocr6frksEqaCBa3ik6nHbbXP2q-N68wd5Aya_RL4</recordid><startdate>20081028</startdate><enddate>20081028</enddate><creator>ROUMBAKIS MENAS</creator><creator>PHAM NAM HUU</creator><creator>CASES MOISES</creator><creator>DE ARAUJO DANIEL N</creator><scope>EVB</scope></search><sort><creationdate>20081028</creationdate><title>Apparatus, system, and method for modifying memory voltage and performance based on a measure of memory device stress</title><author>ROUMBAKIS MENAS ; PHAM NAM HUU ; CASES MOISES ; DE ARAUJO DANIEL N</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7444490B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>PULSE TECHNIQUE</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>ROUMBAKIS MENAS</creatorcontrib><creatorcontrib>PHAM NAM HUU</creatorcontrib><creatorcontrib>CASES MOISES</creatorcontrib><creatorcontrib>DE ARAUJO DANIEL N</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ROUMBAKIS MENAS</au><au>PHAM NAM HUU</au><au>CASES MOISES</au><au>DE ARAUJO DANIEL N</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Apparatus, system, and method for modifying memory voltage and performance based on a measure of memory device stress</title><date>2008-10-28</date><risdate>2008</risdate><abstract>An apparatus, system, and method are disclosed for modifying memory device timing and voltage. A detection module detects a change of memory device stress. A timing modification module modifies the memory device timing in response to the change of the memory device stress. In addition, a voltage modification module modifies the memory device voltage in response to the change of the memory device stress. In one embodiment, a processor pause module pauses the operation of a processor module while the timing modification module modifies the memory device timing and the voltage modification module modifies the memory device voltage.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY INFORMATION STORAGE PHYSICS PULSE TECHNIQUE STATIC STORES |
title | Apparatus, system, and method for modifying memory voltage and performance based on a measure of memory device stress |
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