Power control in a data flow processing architecture

Method and system for dynamically adjusting performance of circuitry blocks are described. A first circuit domain is coupled to an interim storage device. The first circuit domain includes a first level shifter coupled to an input of a first circuitry block and a second level shifter coupled to an output of the first circuitry block. The second level shifter is coupled between the output of the first circuitry block and an input of the interim storage device. A controller is coupled to the first circuit domain for adjustment of a first operating voltage of the first circuit domain.