Use of I2C programmable clock generator to enable frequency variation under BMC control

The present invention provides systems and methods for performing frequency margin testing of a computer system, such as a server. A system of the invention can include a controller, e.g., a BMC, internal to the computer system and a digital frequency synthesizer that can communicate with the controller and can apply clock frequency to marginable components of the computer system. In response to commands from the controller, the synthesizer generates one or more test frequencies that are applied to one or more of the marginable components. The response of the system to each of the test frequencies is then monitored.