Method and mechanism for performing DRC processing with reduced passes through an IC design

Method and mechanism for performing DRC processing with reduced passes through an IC design

A method and mechanism is disclosed for performing a spacing rule DRC check that does not require an excessive number of passes through the IC design. In one approach, a two-pass approach is employed to perform a spacing check. In an approach, a polygons are associated with a family of related polyg...

Ausführliche Beschreibung

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Bibliographische Detailangaben
1. Verfasser: CADOURI EITAN
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:A method and mechanism is disclosed for performing a spacing rule DRC check that does not require an excessive number of passes through the IC design. In one approach, a two-pass approach is employed to perform a spacing check. In an approach, a polygons are associated with a family of related polygons.