Asynchronous sampling rate converter and method for audio DAC

A sample rate converter suitable for use in an audio DAC includes a first estimating circuit ( 32 A) generating first (TR) and second (STAMPR) signals synchronized to an asynchronous clock (MCLK) and representing the period and edge arrival times, respectively, of a reference clock (REFCLK). A second estimating circuit ( 32 B) operates on the first and second signals to generate third (T 1 ) and fourth (STAMP 1 ) signals representing an input sample rate (32fsin) and arrival times of input data samples, respectively, which are applied to a coefficient and address generator ( 76 ) to generate read addresses and coefficients input to a FIFO memory ( 42 ) receiving digital input data at the input sample rate and a multiplication/accumulation circuit ( 78 ) receiving data from the FIFO memory. The multiplication/accumulation circuit produces an output signal (SRC-out) synchronized to the asynchronous clock at an output sample rate (32fsout).