Method and structure for charge dissipation in integrated circuits

Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.