Semiconductor memory

A non-volatile semiconductor memory ( 30 ) comprising a semiconductor substrate ( 1 ) and a plurality of memory cells ( 19 ) and methods for manufacturing such a memory is provided. Each memory cell ( 19 ) comprises a charge-trapping element ( 5 ), a gate stack ( 20 ), nitride spacers ( 10 ) and electrically insulating elements ( 21 ). The charge-trapping element ( 5 ) is arranged on the semiconductor substrate ( 1 ) and comprises a nitride layer ( 3 ) sandwiched between a bottom oxide layer ( 2 ) and a top oxide layer ( 4 ), the charge-trapping element ( 5 ) having two lateral sidewalls ( 24 ) opposed to one another. The gate stack ( 20 ) is arranged on top of the charge-trapping element ( 5 ), the gate stack having two lateral sidewalls ( 25 ) opposing one another. The electrically insulating elements ( 21 ) are disposed at opposing sidewalls ( 24 ) of the charge-trapping element ( 5 ) and cover the sidewalls ( 24 ) of the charge-trapping element ( 5 ). The nitride spacers ( 10 ) cover the electrically insulating elements ( 21 ) and are arranged on opposing sidewalls ( 25 ) of the gate stack ( 20 ) and on the electrically insulating elements ( 21 ).