Parallel path alignment method and apparatus
A method for aligning parallel path data bit streams that may contain skewed data between bit streams and an integrated circuit are disclosed. The method includes, for each bit stream, sampling P data presented on a positive edge of a clock, sampling N data presented on a negative edge of the clock,...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | A method for aligning parallel path data bit streams that may contain skewed data between bit streams and an integrated circuit are disclosed. The method includes, for each bit stream, sampling P data presented on a positive edge of a clock, sampling N data presented on a negative edge of the clock, and delaying the sampled P and N data by one of zero, one-half, one, or other multiple of one-half clock cycle. Delaying the sampled P and N data by one of zero, one-half, one, or other multiple of one-half clock cycle is selected to remove any skew and aligns the sampled P and N data between bit streams. |
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