General purpose delay logic

A logic circuit for delaying a signal input thereto by a number of clock cycles X is described. In one embodiment, the logic circuit comprises a demultiplexer ("DEMUX") which includes an input for receiving the signal and N outputs; a register array comprising at least X registers, wherein...

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Bibliographische Detailangaben
1. Verfasser:	JOHNSON TYLER JAMES
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS PULSE TECHNIQUE SEMICONDUCTOR DEVICES TESTING
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Beschreibung
Zusammenfassung:	A logic circuit for delaying a signal input thereto by a number of clock cycles X is described. In one embodiment, the logic circuit comprises a demultiplexer ("DEMUX") which includes an input for receiving the signal and N outputs; a register array comprising at least X registers, wherein each of the N outputs of the DEMUX is connected to a corresponding one of the X registers; and a multiplexer ("MUX") comprising M inputs, wherein each of the M inputs is connected to one of the registers.