Soft error resistant memory cell and method of manufacture
A semiconductor device memory cell ( 100 ) can include a built-in capacitor for reducing a soft-error rate (SER). A memory cell ( 100 ) can include a first inverter ( 102 ) and second inverter ( 104 ) arranged in a cross-coupled configuration. A capacitor ( 110 ) can be coupled between a first stora...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | A semiconductor device memory cell ( 100 ) can include a built-in capacitor for reducing a soft-error rate (SER). A memory cell ( 100 ) can include a first inverter ( 102 ) and second inverter ( 104 ) arranged in a cross-coupled configuration. A capacitor ( 110 ) can be coupled between a first storage node ( 106 ) and second storage node ( 108 ). A capacitor ( 110 ) can be a "built-in" capacitor formed with interconnect wirings utilized to connect memory cell circuit components. |
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