System and method for modeling, abstraction, and analysis of software

A system and method is disclosed for formal verification of software programs that advantageously translates the software, which can have bounded recursion, into a Boolean representation comprised of basic blocks and which applies SAT-based model checking to the Boolean representation.

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Bibliographische Detailangaben
Hauptverfasser: YANG ZIJIANG, ASHAR PRANAV N, IVANCIC FRANJO, GANAI MALAY, GUPTA AARTI
Format: Patent
Sprache:eng
Schlagworte:
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Beschreibung
Zusammenfassung:A system and method is disclosed for formal verification of software programs that advantageously translates the software, which can have bounded recursion, into a Boolean representation comprised of basic blocks and which applies SAT-based model checking to the Boolean representation.