Zero cancellation in multiloop regulator control scheme

Control loops in a voltage regulator can be stabilized using minimal silicon area. A current limit signal, generated by a current limit control loop in the voltage regulator, can be divided to minimize a zero provided in a compensation set associated with a voltage control loop, thereby stabilizing both loops. The compensation set can include a resistor (the zero) and a capacitor (a pole) connected in series between output and input terminals of an amplifier. Dividing the current limit signal can include injecting a first portion of the current limit signal on a first side of the resistor and injecting a second portion of the current limit signal on a second side of the resistor. The ratio of the first and second portions can be based on a gain of the amplifier, thereby minimizing an effect of the resistor.