Stacked capacitor and method of fabricating same

The invention relates to a stacked capacitor ( 10 ) comprising a silicon base plate ( 16 ), a poly-silicon center plate ( 32 ) arranged above the base plate ( 16 ), a lower gate-oxide dielectric ( 26 ) arranged between the base plate ( 16 ) and the center plate ( 32 ), a cover plate ( 36 ) made of a metallic conductor and arranged above the center plate ( 32 ), and an upper dielectric ( 34 ) arranged between the center plate ( 32 ) and the cover plate ( 36 ). The cover plate ( 36 ) and the base plate ( 16 ) are electrically connected to each other and together form a first capacitor electrode. The center plate ( 32 ) forms a second capacitor electrode. The invention further relates to an integrated circuit with such a stacked capacitor, as well as to a method for fabrication of a stacked capacitor as part of a CMOS process.