Testing of ECC memories

A BIST system that utilizes ECC to correct single bit errors in a given memory word at a given address, the ECC having a maximum number of bit errors it can correct in the given memory word. A first set of gates is coupled to an array of memory cells that stores a plurality of memory words, each at...

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Bibliographische Detailangaben
Hauptverfasser:	VON REYN TIMOTHY J, SALEM GERARD M, ADAMS R. DEAN
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS SEMICONDUCTOR DEVICES STATIC STORES TESTING
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Beschreibung
Zusammenfassung:	A BIST system that utilizes ECC to correct single bit errors in a given memory word at a given address, the ECC having a maximum number of bit errors it can correct in the given memory word. A first set of gates is coupled to an array of memory cells that stores a plurality of memory words, each at a given address. The first set of gates provides bit outputs indicative of errors in a given memory word while the given memory word is under test. A circuit coupled to respective outputs of the first set of gates determines if a number of errors in the memory word under test exceeds the maximum number of errors correctable by the ECC.