Linearization circuit with digital element matching for digital-to-analog converters

A linearization circuit with digital element matching for digital-to-analog converters includes an n-bit delta-sigma modulator that receives an input signal and provides a modulated n-bit signal. An encoder receives the modulated n-bit signal and provides an encoded signal (X) having 2n signal components (x 0, x 1, . . . , x 2 n-1). 2n digital-to-analog converter elements each receive an associated one of the 2n signal components (x 0, x 1, . . . , x 2 n-1) and provide an associated analog signal component (a 0, a 1, . . . , a 2 n-1) indicative thereof. A summer receives and sums the analog signal components to provide an analog output signal. A weighting factor supply device provides a first weighting factor (W+) for activated ones of the digital-to-analog converter elements and a second weighting factor (W-) for non-activated ones of the digital-to-analog converter elements, where the encoder is responsive to the first and second weighting factors.