Method and system for performing functional verification of logic circuits

A method, a computer program product and a system for performing functional verification logic circuits. The invention enables the functional formal verification of a hardware logic design by replacing the parts that cannot be formally verified easily. In one form the invention is applied to a logic design including a multiplier circuit. The multiplier is replaced ( 51 ) by pseudo inputs. The input signal values of the multiplier circuit are determined ( 54 ) automatically from a counterexample ( 53 ) delivered ( 52 ) by a functional formal verification system for a modified design where the multiplier is replaced by pseudo signals. The input signal values are combined ( 55 ) with other known inputs to form a test case ( 56 ) file that can be used by a logic simulator to analyse the counterexample ( 52 ) on the unmodified hardware design including the multiplier.