Clearance hole size adjustment for impedance control in multilayer electronic packaging and printed circuit boards

The present invention provides a technique for adjusting the size of clearance holes for impedance control in multilayer electronic packaging and printed circuit boards. The method comprises: providing parameters for a structure having a clearance hole and at least one via passing through the cleara...

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Bibliographische Detailangaben
Hauptverfasser:	PILLAI EDWARD R, LAFONTANT GARY, DYCKMAN WARREN D
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CALCULATING CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PHYSICS PRINTED CIRCUITS RESONATORS
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Beschreibung
Zusammenfassung:	The present invention provides a technique for adjusting the size of clearance holes for impedance control in multilayer electronic packaging and printed circuit boards. The method comprises: providing parameters for a structure having a clearance hole and at least one via passing through the clearance hole; calculating a characteristic impedance for the at least one via; and adjusting at least a size of the clearance hole until the characteristic impedance for the at least one via is approximately equal to a desired characteristic impedance.