Byte slice based DDR timing closure

Byte slice based DDR timing closure

Presented herein is a system and method for byte slice based DDR timing closure. In one embodiment, there is presented a method for synthesizing/laying out a dual data rate memory, said method comprising synthesizing/laying out a portion of the dual data rate memory; replicating the portion; and pla...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: D'LUNA LIONEL, HUGHES TOM, RADHAKRISHNAN SATHISH KUMAR
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:Presented herein is a system and method for byte slice based DDR timing closure. In one embodiment, there is presented a method for synthesizing/laying out a dual data rate memory, said method comprising synthesizing/laying out a portion of the dual data rate memory; replicating the portion; and placing the synthesized/laid out portion and the replicated portions in proximity to a corresponding plurality of pads.