Interface for a programmable logic device
The present invention provides circuitry for implementing a multiple data rate interface architectures for programmable logic devices. The programmable logic device of the invention includes a core and surrounding periphery. The core includes a plurality of logic elements arranged in an array. Some...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | The present invention provides circuitry for implementing a multiple data rate interface architectures for programmable logic devices. The programmable logic device of the invention includes a core and surrounding periphery. The core includes a plurality of logic elements arranged in an array. Some of the logic elements within the core include registers that are used as data registers for the multiple data rate interface. |
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